Command-Line Interface

HDL Testbench Generator

usage: hdltbgen [-h] -f FILE -t TYPE [-o OUTPUT] [-c CLOCK]
                [-rn RESET_NEGATIVE] [-rp RESET_POSITIVE] [-v] [-s] [-a]

Named Arguments

-f, --file

Name of the VHDL file

-t, --type

Type of testbench (vhdl, csv, excel) (Multiple types can be provided)

-o, --output

Output folder (Default folder of input file)

-c, --clock

Name of the clock (Multiple clocks can be provided)

-rn, --reset-negative

Negative reset (Multiple resets can be provided)

-rp, --reset-positive

Positive reset (Multiple resets can be provided)

-v, --vunit

Generate VUnit testbench

Default: False

-s, --simfile

Generate separate sim-top-file

Default: False

-a, --ask

Ask for values of generics/parameters

Default: False